CUDA programs for solving the time-dependent dipolar Gross-Pitaevskii equation in an anisotropic trap

In this paper we present new versions of previously published numerical programs for solving the dipolar Gross-Pitaevskii (GP) equation including the contact interaction in two and three spatial dimensions in imaginary and in real time, yielding both stationary and non-stationary solutions. New versions of programs were developed using CUDA toolkit and can make use of Nvidia GPU devices. The algorithm used is the same split-step semi-implicit Crank-Nicolson method as in the previous version (R. Kishor Kumar et al., Comput. Phys. Commun. 195, 117 (2015)), which is here implemented as a series of CUDA kernels that compute the solution on the GPU. In addition, the Fast Fourier Transform (FFT) library used in the previous version is replaced by cuFFT library, which works on CUDA-enabled GPUs. We present speedup test results obtained using new versions of programs and demonstrate an average speedup of 12 to 25, depending on the program and input size.Comment: 7 pages, 2 figures; to download the programs, click other formats and download the sourc

Leveraging Interdisciplinary Education Toward Securing the Future of Connected Health Research in Europe: Qualitative Study

Background: Connected health (CH) technologies have resulted in a paradigm shift, moving health care steadily toward a more patient-centered delivery approach. CH requires a broad range of disciplinary expertise from across the spectrum to work in a cohesive and productive way. Building this interdisciplinary relationship at an earlier stage of career development may nurture and accelerate the CH developments and innovations required for future health care. Objective: This study aimed to explore the perceptions of interdisciplinary CH researchers regarding the design and delivery of an interdisciplinary education (IDE) module for disciplines currently engaged in CH research (engineers, computer scientists, health care practitioners, and policy makers). This study also investigated whether this module should be delivered as a taught component of an undergraduate, master’s, or doctoral program to facilitate the development of interdisciplinary learning. Methods: A qualitative, cross-institutional, multistage research approach was adopted, which involved a background study of fundamental concepts, individual interviews with CH researchers in Greece (n=9), and two structured group feedback sessions with CH researchers in Ireland (n=10/16). Thematic analysis was used to identify the themes emerging from the interviews and structured group feedback sessions. Results: A total of two sets of findings emerged from the data. In the first instance, challenges to interdisciplinary work were identified, including communication challenges, divergent awareness of state-of-the-art CH technologies across disciplines, and cultural resistance to interdisciplinarity. The second set of findings were related to the design for interdisciplinarity. In this regard, the need to link research and education with real-world practice emerged as a key design concern. Positioning within the program context was also considered to be important with a need to balance early intervention to embed integration with later repeat interventions that maximize opportunities to share skills and experiences. Conclusions: The authors raise and address challenges to interdisciplinary program design for CH based on an abductive approach combining interdisciplinary and interprofessional education literature and the collection of qualitative data. This recipe approach for interdisciplinary design offers guidelines for policy makers, educators, and innovators in the CH space. Gaining insight from CH researchers regarding the development of an IDE module has offered the designers a novel insight regarding the curriculum, timing, delivery, and potential challenges that may be encountered

Tailor: Altering Skip Connections for Resource-Efficient Inference

Deep neural networks use skip connections to improve training convergence. However, these skip connections are costly in hardware, requiring extra buffers and increasing on- and off-chip memory utilization and bandwidth requirements. In this paper, we show that skip connections can be optimized for hardware when tackled with a hardware-software codesign approach. We argue that while a network's skip connections are needed for the network to learn, they can later be removed or shortened to provide a more hardware efficient implementation with minimal to no accuracy loss. We introduce Tailor, a codesign tool whose hardware-aware training algorithm gradually removes or shortens a fully trained network's skip connections to lower their hardware cost. Tailor improves resource utilization by up to 34% for BRAMs, 13% for FFs, and 16% for LUTs for on-chip, dataflow-style architectures. Tailor increases performance by 30% and reduces memory bandwidth by 45% for a 2D processing element array architecture

Zuclopenthixol decanoate in pregnancy: Successful outcomes in two consecutive off springs of the same mother

Introduction. Almost all individual antipsychotics are classified into the intermediate pregnancy risk category as no or limited data exist about human pregnancy outcomes. We presented the case of zuclopenthixol decanoate using in two successive pregnancies of the same woman, which had not been published in the available peer-reviewed literature. Case report. A middle-age female subject who suffered from schizophrenia received zuclopenthixol decanoate injection during her two consecutive pregnancies. About four and a half months before diagnosis of the first pregnancy (~3.5 years after psychosis emergence), zuclopenthixol decanoate (400 mg every other week, im injection) was introduced to the treatment protocol (due to previous non-compliance with halo-peridol and risperidone). A significant clinical improvement was achieved and the dose during pregnancy was reduced to 200 mg once monthly and maintained to date. In both pregnancies the women gave birth to healthy girls who have been developing normally until now, at their ages of 6 months and of 3.5 years. During pregnancy and after giving birth to children the mothers' psychiatric status and her social functioning were significantly improved and are still stable. Close monitoring of the mother's health, a multidisciplinary approach to both her treatment and the monitoring of pregnancies as well as the complete compliance with the prescribed drug protocol were likely to be crucial for the therapeutic success. Conclusion. A favorable outcome of the present case suggests that the zuclopenthixol decanoate is a rational therapeutic option for pregnant women suffering from psychosis when the expected benefit exceed the potential risk, but a definitive evidence for its safety requires large, controlled studies

Automatic heterogeneous quantization of deep neural networks for low-latency inference on the edge for particle detectors

Although the quest for more accurate solutions is pushing deep learning research towards larger and more complex algorithms, edge devices demand efficient inference and therefore reduction in model size, latency and energy consumption. One technique to limit model size is quantization, which implies using fewer bits to represent weights and biases. Such an approach usually results in a decline in performance. Here, we introduce a method for designing optimally heterogeneously quantized versions of deep neural network models for minimum-energy, high-accuracy, nanosecond inference and fully automated deployment on chip. With a per-layer, per-parameter type automatic quantization procedure, sampling from a wide range of quantizers, model energy consumption and size are minimized while high accuracy is maintained. This is crucial for the event selection procedure in proton-proton collisions at the CERN Large Hadron Collider, where resources are strictly limited and a latency of ${\mathcal O}(1)~\mu$s is required. Nanosecond inference and a resource consumption reduced by a factor of 50 when implemented on field-programmable gate array hardware are achieved